Wednesday, 20 September 2017

DVCON-17 India: Post Conference Updates

Hi Readers,

  Attended 4th Edition of DVCON-17 India on Sep 14th & 15th in Bangalore.Summarizing the key highlights  below.

 DVCON India got an outstanding response with houseful gathering of DV Engineers, It started  with keynote speeches followed by  Tutorials and Panel Discussions on current topics like Machine Learning, Emulation,PSS, etc.The day ended with a Gala Dinner and created an opportunity to meet peers from other companies.

Day 2 stared with a keynote speech on "Driving the Next Big Wave in Verification by Ravi Subramanian from Mentor Graphics followed by paper and poster sessions.

There were handful papers on UVM, attended below papers in the UVM Track. 

  1. How to inject errors in UVM RAL:  Explained by using callbacks
  2. Adopting UVM for FPGA  & RTL Engineers:  Explained about go2uvm app 
  3. Real world clock generator: Explained on how to develop a clock agent with all possible options like jitter etc…
  4. Embedded UVM: Explained how to use it on raspberry pi
  5. The coverage generator: script to automate functional coverage coding

I have presented 2 papers as mentioned below.
1. Trials and Tribulations of migrating a native UVM Testbench from Simulation to Emulation
2.    A 360 view of UVM Events

 Got good response from the audience, The full paper can be found in DVCON-17 archives shortly.


Image may contain: one or more people, screen and indoor

Conference provided networking opportunities , met some old friends and made new friends as well, also learnt new technologies. Meet you again in DVCON-18.

Happy Reading..!

Vikas Billa 

Saturday, 3 December 2016

Mentors Graphics U2U Conference, Dec - 2 2016, Bangalore : Updates

Hi Readers,

  Attended Mentor Graphics User 2 User 2016 on Dec 2, Bangalore. Summarizing the same below

 U2U India got an outstanding response with houseful gathering of VLSI Engineers, Conference started  with Welcome speech by Ruchir Dixit, Technical Director,  on Congnitive shift to transformative Decisions - briefed on the adoption of new technologies , explained using some general examples as shown below.

 Figure 1: Ajay to Dhoni as wicket keeper for Indian cricket Team.

Later Walden Rhines, Chairman, given a keynote on Next wave of semiconductor Growth with actual data vs  predicted growth data  from previous years.

Industry keynote speech on "Make In India" is delivered by Kiron shah , MD , Velankani Group, he played a video which showed his achievements from last 9 months..from setting up plant to shipping etc..

Latter Attended sessions in Functional Verification Track. There were 8 papers in this session on Qformal, Veloce and QVIP etc..

We have presented 2 papers on Qformal from our company, I was co-author for one of the paper titled " Using Questa Formal Connect Flow to Improve Quality and Productivity".

  Figure 2:  U2U Slide 

We got an outstanding response from the audience, The full paper can be found in U2U archives shortly.


Conference provide lot of networking opportunities , met some old friends and made new friends as well, besides learning new technologies. wishing you to meet you again in next U2U - 2017.

Happy Reading..!

Vikas Billa 

Wednesday, 26 October 2016

DVCon -16, USA papers are available now for download.

DVCon -16, USA papers are available now for download.

Please download our paper and presentation on "UVM_Events"

Please write to us for suggestions/comments.

Happy Reading,
Vikas Billa

Sunday, 3 July 2016

Wednesday, 22 June 2016

The Overlooked Gems of UVM : UVM Report Catcher, UVM Heartbeat and UVM Events

This paper is submitted for 53rd Design Automation Conference , please find the slides for the same.

1.       Report catcher file.

class error_report_catcher_c extends uvm_report_catcher;
  //new constructor
  virtual function action_e catch();
    if(get_severity() == UVM_ERROR && get_id() == "MON_CHK_NOT_VALID") begin
      return CAUGHT;
    else begin
      return THROW;
endclass : error_report_catcher_c


class invalid_test extends base_test_c;

  // report catcher to suppress errors
  error_report_catcher_c error ;
  /// \fn new_constructor
  /// \fn build_phase
virtual function void build_phase(uvm_phase phase);
      error = new();
      uvm_report_cb::add(null,error) ;
      // User configurations
      uvm_config_db#(env_config_c)::set(this, "*" , “env_cfg", env_cfg);
      // Calling the error sequence
      uvm_config_db#(uvm_object_wrapper)::set(this, “uvc.tx_agent.tx_sequencer.main_phase","default_sequence",valid_invalid_seq_c::type_id::get());
  endfunction : build_phase

endclass : invalid_test

Typically an ASIC or a SOC will have multiple resets and which adds other dimension to reset verification wherein verification engineer need to ensure that the modules in the chip react only to the desired resets and ignore others. On-the-fly reset must be taken into account by all the modules of testbench and housekeeping must be made accordingly.

Figure I is a representation of stimulus life-span and flow in a reset aware test-bench. Apart from reset agent, the Verification environment has two other agents which can be reset individually by applying agent1 reset or agent2 reset respectively, or simultaneously by applying a global reset. Reset agent from Figure I will be continuously monitoring the reset interface and triggers the reset event on successful capture of any of the above mentioned resets. All other components in the test bench will waiting for a respective reset even trigger.

 Here is how the 4 major components Drive, Monitor, Scoreboard and Sequences must behave on capturing the reset event:

1) Must not drive data under reset and wait until reset is removed.  (t4 from figure 1)
2) Must stop driving the bus and send item_done on reset application. (t4 from figure 1)
3) Must complete the transaction if there was no reset while the transaction is in progress.(t5 and t6 from figure 1)

1) Must be monitoring the bus and trigger report error for conditions on bus which are not expected under reset. (t4 from figure 1)
2) Must treat the bus data as invalid if a reset is applied in between a transaction. (t4 from figure 1)

1) On application of the reset all the FIFO’s must be flushed. (t4 from figure 1)

1) Immediately after reset the configuration sequence must be driven before driving any other sequence. (t6 from figure 1)

Reset is an important state of an IP and the test-bench needs to be designed to accommodate and handle this state. Here are simple steps with code samples to make your test-bench reset-aware:

Triggering interrupts from sequences:
As a part of stimulus

Triggering a global reset event:
global_reset_ev = cfg.event_pool.get(“global_reset”);
In case of Agent1 reset:          

Triggering an Agent1 reset event:
agent1_reset_ev = cfg.event_pool.get(“agent1_reset”);      

Triggering an Agent2 reset event:
agent2_reset_ev = cfg.event_pool.get(“agent2_reset”);      

In reset aware components: Components shall wait for respective interrupts and implement their reset behavior upon successful reception of interrupts.

forever begin : Reset_service
   fork   : capture_reset

The on-the-fly reset can be made more elegant by usage of customized uvm_phases, this approach is out of this paper scope.

Happy Reading ...!

Monday, 20 June 2016

VLSI Workshop

I got an opportunity to speak with the budding engineers on VLSI and it's Job opportunities.

please click on the below link for the slides.

Workshop Slides

Workshop Pics:

Will upload the Audio soon.