Monday, 30 May 2016

System Verilog : Soft Constraints


 Soft constraints are default constraints which hold true until contradicted by another similar constraint.



Let us understand this concept with the following examples.

1.    We have a packet class with address variable, which is limited in between 10 and 100.

class packet;
 
  rand bit[7:0] address;
 
  constraint address_c {
    address inside {[10:100]};
  }
 
endclass

program test();
 
  packet p;
 
  initial begin
    p=new();
    assert(p.randomize());
    $display("address value is %0d" , p.address);
  end
 
endprogram


Output:  address value is 53


The output is 53 which is in between 10 and 100.

2.   Let us apply a inline constraint stating that address should be equal to 200.


class packet;
 
  rand bit[7:0] address;
 
  constraint address_c {
    address inside {[10:100]};
  }
 
endclass

program test();
 
  packet p;
 
  initial begin
    p=new();
    assert(p.randomize() with { p.address==200;} );
    $display("address value is %0d" , p.address);
  end
 
endprogram

Output: Error

Error-[CNST-CIF] Constraints inconsistency failure
testbench.sv, 19
  Constraints are inconsistent and cannot be solved.
  Please check the inconsistent constraints being printed above and rewrite
  them.

"testbench.sv", 19: test.unnamed$$_3.unnamed$$_1: started at 0ns failed at 0ns
                Offending 'p.randomize() with {
(p.address == 8'hc8);
}
'
address value is 0

The output is 0, here the randomization failed due to constraint conflict i.e. we have given an inline value for address which is out of the range i.e. in between 10 to 100, in such scenarios we need to switch off the corresponding constraints as shown below.

 class packet;
 
  rand bit[7:0] address;
 
  constraint address_c {
    address inside {[10:100]};
  }
  Which
endclass

program test();
 
  packet p;
 
  initial begin
    p=new();
    p.address_c.constraint_mode(0);
    assert(p.randomize() with { p.address==200;} );
    $display("address value is %0d" , p.address);
  end
 
endprogram


output: address value is 200

3.  Let us change the code slightly and use soft keyword before address variable in constraint block as shown below.

class packet;
 
  rand bit[7:0] address;
 
  constraint address_c {
    soft address inside {[10:100]};
  }
 
endclass

program test();
 
  packet p;
 
  initial begin
    p=new();
    //p.address_c.constraint_mode(0);
    assert(p.randomize() with { p.address==101;} );
    $display("address value is %0d" , p.address);
  end
 
endprogram


output: address value is 101


In the above code there is no need to use additional constructs like constraint_mode(0) , here the inline constraint of {p.address == 101 } will have the priority and the solver solves this instead of above declarative constraint ( constraint address_c { soft address inside {[10:100]};  } )

These soft constraints can be used to check the error/illegal scenarios.
 
 So the output here is 101.


 Happy Learning.

 Please provide your feedback if any.

Thanks,
Vikas Billa


Thursday, 31 March 2016

DVCON-16 Paper : A 360 Degree View of UVM Events : Presentation Slides

Paper A 360 Degree View of UVM Events

Presenting you the highlight slides for reference.

For full paper and presentation slide please do write to us.






























Saturday, 27 February 2016

Solar System and Verification IP

The right process for a verification IP development is planning, development and closure. These steps are compared with the planets of a solar system. Each step in VIP development is assigned with a planet as explained below.

Figure 1: Solar System

Solar System
Verification IP
Sun
DUT
Mercury
Verification Plan
Venus
Agents Development
Earth
Testbench Development
Mars
Assertions and Functional Coverage Development
Jupiter
Test Cases Development
Saturn
Regression and Debug
Uranus
Fixing Testbench or Test cases
Neptune
Coverage Closure
Pluto
Release – User guide, Product Documents etc...

Table 1: Verification IP compared with Solar System

Further to above planets there are scary looking asteroids in solar system which are treated as bugs. These bugs may be DUT bugs or Testbench bugs.

                                        Figure 2:  Verification IP Development Steps

Thursday, 14 January 2016

DAC - 15 : Poster Presentations

Please find the posters from the below link.

Paper Title: VIP Development Techniques – A view into Controlling Features Effectively

Link: VIP_Development_Techniques.pdf

Abstract:  VIPs offer range of benefits including reusability aspects, plug and play features and providing all the necessary hooks and functionalities in a single entity with a standard framework.

The standard framework (Driver, Monitor and Sequencer) has evolved over a decade as part of the methodology developments and enhancements.

We can argue that feature segregation between VIP components depends upon protocols/standards. However there are common aspects which one need to be aware of and are important for controlling the flow of information within and outside the VIP.

This paper presentation highlights some of those techniques focused on ACTIVE path (Interactions between driver and sequence item) of the Verification IP.


Paper Title: Developing Common UVM Testbench for Simulation and Emulation Platforms to Reduce Verification Effort Across Different Abstraction Levels

Link: Abstarction_Levels.pdf

Abstract: Today’s traditional verification flow involves verification at multiple levels of abstraction. So the testbench also needs to be adjusted/modified at different abstractions from transaction-level simulation, RTL simulation to hardware acceleration.

An ideal solution is to make use of an advanced, automated verification environment across different abstraction levels, which helps in enhancing the overall performance gain, productivity and faster verification closure.


Thanks for reading, please inbox me for any queries/suggestions



Friday, 8 January 2016

DVCON -15 India : A Reusability Combat in UVM : Callbacks vs Factory

Please find the poster at the below  link

UVM_Callbacks_vs_Factory.pdf



If you need full length paper or if you have any Questions please inbox me.

Saturday, 27 June 2015

Insertion of Pragmas in Source Code using Cshell Script

Their was a requirement to develop a script to add pragma to the code in order to encrypt the source code.We need to add `protect begin and `protect end between module and end module of .v files.



Original .v file:

 module chip( MINUS,PLUS );

  output wreal PLUS;
  input wreal MINUS;

  parameter elite  = 0;
   parameter coffee = 1;
   parameter club   = 1;

  always@(*) 
   begin 
    $display("elite  = %d" , elite );
    $display("coffee = %d" , coffee);
    $display("club   = %d" , club  );
   end

endmodule 
// comments 
// parameter

Output .v file:

 module chip( MINUS,PLUS );

  output wreal PLUS;
  input wreal MINUS;

  parameter elite  = 0;
   parameter coffee = 1;
   parameter club   = 1; 

  `protect begin

  always@(*) 
   begin 

    $display("elite  = %d" , elite );
    $display("coffee = %d" , coffee);
    $display("club   = %d" , club  );
   end

 `protect end

endmodule
// comments 
// parameter



The script was written in cshell as stated below

#! /bin/csh -fx

setenv RUN_DIR $PWD

set filename = $RUN_DIR/test_list.txt  # test_list.txt gives list of all .v files
set temp = temp                        # temp variable
set file = file                        # file variable

foreach filelocal (`cat $filename`)    # foreach is reading each file in test_list

  echo $filelocal

  # Removing Tempfiles
  rm -rf $file$temp                    # Removing temporary in between generated files
  rm -rf $file

  # Removing comments in the file
  cat $filelocal | sed 's/\/\/.*$//' > $file  # Making sure to remove all comment " // " lines from the orginal .v file ($filelocal) and piping to a temporary file ($file)

  #Counting total lines of the file
  set count = `cat $file | wc -l`             # counting the entire lines of the file ($file)

  # Finding the last line for the grep item
  set final = `grep -n "input\|output\|parameter\|inout" $file | sed 's/:/ /g' | awk '{print $1}' | tail -n 1 `  # Here we are greping the various fields as stated , here up to parameter and finding the line number


  echo $final

  head -$final $file > $file$temp # Then we are sending the contents of the lines up to the parameter to a new file

  echo \`protect begin >> $file$temp # Then printing the `protect begin to the new file

  # Finding the last line for the grep item
  set end = `grep -n "endmodule" $file | sed 's/:/ /g' | awk '{print $1}' | tail -n 1 ` # Finding the endmodule line here
  echo $end

  # printing between Lines
  set final = `expr $final + 1`
  set end = `expr $end - 1`

  sed -n $final,{$end}p $file >> $file$temp # Printing all the lines between after parameter last line to endmoule before line

  echo \`protect end >> $file$temp # Printing the `protect end
  echo endmodule >> $file$temp # Printing endmodule

   #printing end lines
  set end = `grep -n "endmodule" $file | sed 's/:/ /g' | awk '{print $1}' | tail -n 1 `
  set rem = `expr $count - $end`
  tail -$rem $file >> $file$temp # Printing the ending lines after endmdule

  # Copying the local file to orginal file
  cp -rf $file$temp $filelocal  # Copying the temporary file back to original file

end

Thanks for reading this post ..!

Saturday, 13 June 2015

DAC-15 Highlights

Design Automation Conference got an outstanding response, around 800 papers were submitted this year in which 200 papers were finalized.  All keynote presentations were very interesting especially the smart lens  speech by Brain Otis ,Director from Google was really amazing. Vivek Singh speech on Moore’s law at fifty was another highlight , his presentation was outstanding especially the ending slide which shows the Moore Photograph.


My Interaction with Cliff Cummings ( Sunburst Design) , Dave Rich ( Verification Academy) helped me in understanding UVM concepts in depth.



My presentation was satisfactory received positive response from the audience , heard the next big turn in verification is simAccel ( Simulation + Acceleration) and  VIP vendors are about to start this in full-swing.



At last it was a satisfactory trip with thought provoking discussions.